VLSI chip is a very large-scale integrated circuit. It is a mega electronics circuit comprising of millions of transistors to perform an intended fast compute operation. Although it consists of millions of transistors, it looks very small. Transistor is a basic cell of VLSI chip. Transistors are combined together as per the design intent to form a VLSI chip.

System Verilog (SV) is hardware design language. In olden days, electronics circuits were designed manually, which used to be very tedious. With advancement of technologies, System Verilog language is used to design electronics circuits. Hardware design flow looks like software coding. Verilog is similar to C language.

System Verilog supports the following constructs for development of hardware.

Concurrent statements:

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These statements execute concurrently and independently. Always and initial are concurrent statements. Initial block executes only once. Always block will have signals list and it executes whenever value of signals changes.

Example:

//This Always block has sig1 and sig2 in its signals list. It executes whenever sig1 or sig2 changes.

always @ sig1 or sig2

begin

     $display("Print_XYZ");           

end

//This Always block has sig5 and sig6 in its signals list. It executes whenever sig5 or sig6 changes.     

always @ sig5 or sig6

begin

     $display("Print_ABC");           

end

//Initial block executes only once.

initial

begin        

     $display("Print_MNM");

end

Sequential statements:

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These statements execute sequentially. Few examples of sequential statements are conditionals, loops, functions and tasks.

Example:

always @ (sel or sig1 or sig2) // always is a concurrent statement. It executes whenever sel or sig1 or sig2 change

begin                                           // The below statements are sequential statements

     If (sel == 0)                          

         out = sig1;

     else

         out = sig2;    

 end

Conditionals: Conditionals help us make a choice based on conditional expression. If the conditional expression evaluates to true, then that portion of code is executed. If expression evaluates to false, then that portion of code is skipped.

Example:

if (a > 5)

    <code>   //This code executes when expression a>5 is true

else if (b > 100)

    <code>   //This code executes when expression b>100 is true and expression a > 5 is false

else

    <code>   //This code executes when both the expressions are false

Loops: Loops are useful when we need something to happen repeatedly. They help in keeping the code short. Loop executes the series of code multiple times.

Commonly used loop constructs are For Loop and While Loop. “For Loop” executes the code a fixed number of times. “While Loop” executes the code until condition turns false.

Example:

for (int i =0; i<100;i++)  //Executing code for 100 times

begin

      <code>

end

While(expression) //Executing code as long as expression is true

begin

     <code>

end

Functions: Functions are used to avoid rewriting same code again and again in a program. Function contains set of instructions that can be used many times. Rather than write all the instructions every time, we can simply use the name of the function instead, and then the instructions contained within that function will execute on their own.

Example:

function Add_func (int a, int b); //Add_func is function name. This function computes sum of integers a and b.

begin

      int sum; sum = a + b;

      $display (“The sum of a and b =%d”, sum);

end

Logical and Arithmetical Operators: Arithmetical operators are Add/Subtract/Multiply/Division which are used for arithmetic operations. Logical operators Or/And/Not are used for logical operations.

Example:

int sum, num1, num2;

sum = num1 + num2; //sum is the addition of num1 and num2

The following few examples show system-verilog code to create basic electronics circuits.

 assign sum = a + b; // This creates adder circuit: sum being the output And a,b being inputs.

 assign product = a x b;//This creates multiplier circuit

 assign diff = a – b; // This creates subtractor.

 assign result = sel ? a : b; // This create multiplexer which selects a or b based upon “sel” value.

Hardware designing has been simplified with advancements in System Verilog. The design developed in System Verilog is called RTL code. It is thoroughly tested to ensure zero defects. Industry standard simulation tools like cadence simulators are used to test the design. RTL code is transformed to gates or transistors using RTL synthesis process.